LASO-BOSS: LLM-driven Analog Sizing Optimization via Bayesian Optimization and Sizing Strategies

Abstract

Analog circuit sizing is a challenging problem due to its vast design space and the need to optimize multiple, and often conflicting, performance metrics. The design process heavily depends on human expertise, making it both time-consuming and labor-intensive. While recent studies have explored the use of Large Language Models (LLMs) to assist design exploration, these approaches often operate at a lower level (e.g., directly modifying netlists or proposing incremental design points), which necessitates repeated LLM API calls and incurs significant token usage. It is desirable to have smart strategies that can also assist in high-level decision-making, such as generating sizing strategies that effectively reduce the design search space and minimize costly LLM calls. This paper presents LASO-BOSS, an LLM-driven Analog Sizing Optimization via Bayesian Optimization and Sizing Strategies, that uses an LLM to extract hierarchical information about the circuit structure and generate a multi-phase sizing strategy for Bayesian Optimization (BO). By leveraging the LLM's reasoning ability and domain knowledge, LASO-BOSS dynamically narrows the design search space and focuses on specific performance objectives in each phase, enabling more efficient and effective optimization. Experimental results show that LASO-BOSS consistently outperforms state-of-the-art BO baselines, even when operating with less than 50% of the original optimization budget. It also surpasses existing LLM-driven BO methods while dramatically reducing LLM usage, requiring only two API calls and 6× to 45× fewer tokens.