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February 7, 2017
High-Speed Data Readout Minimizes Distortion*2 in Still Images, and Enables Super Slow Motion Movie Shooting
Sony Semiconductor Solutions Corporation
Tokyo, JapanâSony Corporation today announced the development of the industry's first*1 3-layer stacked CMOS image sensor with DRAM for smartphones. The new image sensor consists of a DRAM layer added to the conventional 2-layer stacked CMOS image sensor with a layer of back-illuminated structure pixels and a chip affixed with mounted circuits for signal processing.
This newly developed sensor with DRAM delivers fast data readout speeds, making it possible to capture still images of fast-moving subjects with minimal focal plane distortion*2 as well as super slow motion movies at up to 1,000 frames per second (approximately 8x faster than conventional products*3) in full HD (1920x1080 pixels).
In order to realize the high-speed readout, the circuit used to convert the analog video signal from pixels to a digital signal has been doubled from a 2-tier construction to a 4-tier construction in order to improve processing ability. Although there are speed limitations in the interface specifications for outputting signals from image sensors to other LSIs, this sensor uses DRAM to store signals read at high speed temporarily, enabling data to be output at an optimal speed for the standard specifications. As a result, the product is capable of reading one still image of 19.3 million pixels in only 1/120 of a second (approximately 4x faster than conventional products*3), thereby supporting high-speed image capture.
The newly developed sensor also includes solutions for the various technical problems inherent in the design, for instance, reducing the noise generated between the circuits on each of the three layers. Sony has made the most of the expertise in stacked image sensor manufacturing technology, which it pioneered and developed over the years, to ensure that quality and reliability remains high despite the complex three-layered construction.
These development results were announced at the International Solid-State Circuits Conference (ISSCC) which started on Sunday, February 5, 2017 in San Francisco.
1. Industry's first*1 3-layer stacked configuration with DRAM delivers high-speed readout of 19.3 million pixel image in only 1/120 second
With the stacked high-speed, low power consumption, high-capacity DRAM, the new sensor can read one still image of 19.3 million pixels in only 1/120 second (approximately 4x faster than conventional products*3), reducing the time lapse for reading each pixel line. This technology minimizes the focal plane distortion*2 in still images that tends to occur when shooting fast-moving subjects on smartphones, which lack a mechanical shutter for controlling exposure time.
The high-speed readout capability makes it possible to record up to 1,000 fps (approximately 8x faster than conventional products*3) super slow motion movies in full HD (1920x1080 pixels). Normal speed shooting data and maximum 1,000 fps high-speed shooting data stored on the DRAM are exported from the image sensor for signal processing on an external image signal processor (hereafter referred to as ISP), making it possible to record vibrant movies on a smartphone that seamlessly combine normal speed movies and super slow motion movies. To ensure that users don't miss split-second moments in super slow motion movies, it is possible to adjust settings so that sudden subject movement is automatically detected and high-speed shooting begins. Because high-speed shooting data is stored on the DRAM and output at a normal speed, a conventional ISP can be used.
|Effective pixel count||5520 (H) x 3840 (V) 21.2 megapixels|
|Image size||Diagonal 7.73mm (Type 1/2.3)|
|Unit cell size||1.22μm (H) x 1.22μm (V)|
|Frame rate||Still images||
|Reading speed||8.478 ms (4:3 19.3 megapixels) / 6.962 ms (16:9 17.1 megapixels)|
|Power supply||2.5V / 1.8V / 1.1V|
|Image format||Bayer RAW|
|Output||MIPI (CSI2) D-PHY 2.2Gbps/lane / C-PHY 2.0Gsps/lane|
|DRAM capacity||1G bit|