A 2.1μm High Dynamic Range CMOS Image Sensor with Sub-pixel and Lateral Overflow Integration Capacitor architecture

Abstract

This is a report on a CMOS image sensor using a pixel architecture of 2.1μm Sub-pixel and Lateral Overflow Integration Capacitor (LOFIC) readout, which consists of a large and small PD with intra-pixel capacitance. This sensor has a pixel pitch of 2.1 µm and is equipped with a Sub-Pixel with two photodiodes, one large and one small, and a MOS capacitor Floating Capacitor (FC) and a MOM capacitor Extra Capacitor (EC) in the pixel, and by connecting four signals in a single exposure, it has both a high dynamic range of 105 dB and LED flicker suppression, Motion artifact free.

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Company
Sony Semiconductor Solutions Corporation
Conference
IISW
Year
2025