A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET

Abstract

This paper presents a 28GHz fully differential self-biased clock buffer with an embedded low pass filter (LPF) on the self-bias gates. This LPF shields the gates from the output making the output rising and falling edge transitions steeper while reducing the power consumption. By utilizing several small enable switches as resistors to configure the LPF for small area, it conveniently allows to power down the circuit while preventing a shift in common-mode voltage caused by the voltage drop of a conventional power-gating switch. Fabricated in a 16-nm process with an active area occupation of 105μm², the proposed design at 28GHz operation achieves 19.44fsec rms jitter according to the simulation result while consuming only 5.13mW in the measurement.

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