A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing

Abstract

We propose a magnetic tunnel junction (MTJ)-based nonvolatile SRAM (NVSRAM) to obtain normally off computing. The proposed NVSRAM not only combines SRAM performance and non-volatility but also shows improved area efficiency by sharing the driver with peripheral circuits. Moreover, the data-aware store scheme enables reduction in store energy by data comparison control and a verify operation that mitigates MTJ process variation. We fabricated a 2 kb macro by using a 40 nm process with optimized memory cells to overcome the risk of latch destruction of conventional cells. The measurement results demonstrated a non-volatile function and 3.5x store energy reduction by the store control optimization.

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