Development of A Novel WoWoW Process for 1/1.3-inch 50 Megapixel Three-wafer-stacked CMOS Image Sensor with DNN Circuits

Abstract

The first ever 3-wafer-stacked CMOS image sensor with deep neural network (DNN) circuits was developed. The sensor was fabricated using wafer-on-wafer-on-wafer (WoWoW) process which was composed of 6μm pitch face-to-face and face-to-back Cu-Cu connections and 6μm pitch TSVs. In this study, we report a novel WoWoW process that enables an AI chip with a built-in DNN to be added to the bottom wafer of a conventional high-performance, high-resolution 2-wafer-stacked image sensor. We discuss the improvement of the WoWoW process, the electrical characteristics and reliability and the imaging results of the proposed device.

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