High Full Well Capacity and Low Noise Characteristics in 0.6μm Pixels via Buried Sublocal Connection in a 2-Layer Transistor Pixel Stacked CMOS Image Sensor

Abstract

Ensuring high dynamic range (D-range) in Pixel shrinkage is important for realizing image capture. The pixel shrinkage makes it difficult to ensure high FWC due to the inability to secure PD area and low noise due to the pixel transistors size reduction. A 2-Layer transistor Pixel stacked CMOS image sensor (“2-Layer Pixel”) has been proposed as a promising technology for capturing images with low noise and high D-range and achieving Pixel shrinkage in CMOS image sensors. [1-2] Schematic diagrams of the 2-Layer Pixel are shown in Figs. 1 and 2. The 2-Layer Pixel comprises an Si layer on which the PDs and transfer gates are arranged. A second layer contains the pixel transistors, such as the amplifier transistors, select gates, reset gates, and deep contacts, to connect the PDs and pixel transistors. Additionally, FTIs are formed to separate pixels. In a previous study, we developed a three-dimensional (3D) sequential integration process to realize the 2-Layer Pixel. [2]
This paper presents a 2-Layer Pixel with a 0.6 µm Pixel, an RN of 0.99, an FWC of 8000e-, and a D-range of 78.1 dB. This is achieved by introducing a single vertical transfer gate (SVG), buried sublocal connections (BSCs), and Pixel FinFETs.
The 2-Layer Pixel structure and the introduction of the SVG enlarge the transfer gate (TG) layout area, as shown in Fig. 3(a-c). An FWC of 8000e- was achieved with the SVG by optimizing the geometry and placement of SVG.
We introduced BSCs and Pixel-FinFETs to reduce the RN. Moreover, sublocal connections (SCs) are formed between the first and second layers to reduce the number of deep contacts, as shown in Fig. 4(a)[2]. The contact area is changed from the Si surface to Si sidewall in the developed BSCs, as shown in Fig. 4(b). The FD capacitance is reduced by 46% using the SCs and BSCs. (Fig. 4(c)). The BSCs have ohmic conductivity, and the resistance is plotted in Fig. 4(d). To shrink the FD sharing unit from 2*4 to 2*2, we adopted Pixel-FinFETs. Introducing BSCs and changing the FD sharing unit increased the conversion gain by 2.26 times and decreased the RN by 67%, as shown in Fig. 5(a-b).
We fabricated a 2-Layer Pixel with 0.6 μm photodiodes (PDs), as shown in Fig. 6. Figure 7 shows the relationship between the pixel size and D-range, wherein the FWC and RN of PD CISs reported in previous studies [3-7] are compared with those obtained in this study. The performance parameters and comparison with prior works are summarized in Table Ⅰ. The detailed experimental results will be included in the final.

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