Low Dark Noise and 8.5ke- Full Well Capacity in a 2-Layer Transistor Stacked 0.8μm Dual Pixel CIS with Intermediate Poly-Si Wiring
Abstract
This paper demonstrates a 2-layer stacked 0.8μm dual pixel CMOS image sensor, which is world’s smallest dual pixel. We improved the layout flexibility with Intermediate Poly-Si Wiring technique. Our advanced 2-layer pixel device achieved low random noise of 1.3 e−rms and high full well capacitance of 8.5k e−.
- 著者
- 所属
- Sony Semiconductor Solutions Corporation
- Sony Semiconductor Manufacturing Corporation
- 学会・学術誌
- IEDM
- 年
- 2024
