Low temperature epitaxial SiGe:P for gate-all-around(GAA) nMOS devices

Abstract

This epitaxial also brings new challenges for source/drain (S/D) engineering.In general, SiGe:B for pMOS and Si:P for nMOS are currently utilized for source/drain (S/D) engineering since they allow to achieve high active carrier concentration and low contact resistivity.Recent TCAD simulations about S/D channel strain of GAA show that SiGe:B induces tensile strain, whereas Si:P induces compressive strain in the S/D channel. Therefore, if typical S/D materials areadopted to GAA and CFET, strain in the channel is inverted, causing device characteristic degradation [1].To obtain a correct strain sign that leads to improved electrical properties, we propose to apply Si:B for pMOS and SiGe:P for nMOS. At the same time, the thermal budget impact on the device must be minimized and high active carrier concentration allowing low contact resistivity must be achieved as well. To meet these requirements, we focused on epitaxial growth of SiGe:P at temperatures below 500℃ using high order Si and Ge precursors. We focused on SiGe with Ge concentrations below 30%. Higher Ge% were studied in[2].Here we report on high quality SiGe:P layers with high active carrier concentrations(~2E20(cm³)) grown at low temperatures. Ge concentration was successfully reduced down to ~10% while maintaining a low contact resistivity as demonstrated by Circular-TLM measurement.
[1] G. Eneman et al., 2020 ECS Trans. 98 253
[2] A. Hikavyy et al., 2020 ECS Trans. 98 43