Recent advances in SPAD sensor technology: Pixel size shrinking and PDE enhancement
Abstract
SPAD pixels have been developed for ToF range image sensors [1-3] and photon counting image sensors [4-6] by exploiting its single photon sensitivity and sub-nanoseconds level timing resolution. Recently, back-illuminated SPAD stacked with pixel parallel pixel front-end circuit (PFE) by Cu-Cu connection has been proposed and it allows us to increase the SPAD pixel fill factor and photon detection efficiency (PDE) with shrinking the SPAD pixel size and integrating more advanced pixel-parallel front-end circuits.
Sony semiconductor solutions (Sony) has reported back-illuminated 10 μm SPAD pixel array with over 14% PDE at 940 nm wave length [7] and the its applications for ToF depth sensor [3]. The SPAD pixel comprise 7-μm-thick silicon, on-chip micro-lens (OCL), metal reflector and full trench isolation (FTI) with buried metal. The structure combined with drift potential optimization can improve PDE to 14 % at 940 nm wavelength with suppressing optical crosstalk to 0.30 %. The dark count rate (DCR) is around 3 cps at room temperature and the timing jitter is 173 ps with 3 V excess bias. The LiDAR system for automotive application has been developed by integrating the advanced circuit under the SPAD pixel. The LiDAR system is capable of detecting objects 150m ahead with less than 0.1 % measured error even if the reflectance is less than 10 % under day light.
We have tried to decrease SPAD pixel size to 6 μm [8], 3 μm and 2.5 μm [9] with enhancement of PDE [10]. The peak PDE is increased to 82.5 %, the PDE at 940 nm wavelength is over 26.5 % and DCR is 2.2 cps at room temperature with 3.3 μm pixel and 3V of excess bias. The high PDE is achieved by gapless OCL and pyramid surface for diffraction (PSD) structure. The sufficiently low DCR is achieved by optimizing the multiplication layout design to increase avalanche guard ring width (Fig. 1). The small SPAD improve robustness of depth sensing against ambient light by decreasing count loss under high incident optical power. The PDE at 940 nm wavelength has been further enhanced for 6-μm-pitch pixel to 36.5 % with shallow trench for diffraction (STD), 2 x 2 OCL and optimized PSD and FTI (Fig.2) [10]. The optimized PSD and STD can increase optical path in the SPAD pixel. The 2 x 2 OCL enhance the effect of the STD structure because the 2 x 2 OCL layout well matches to the STD layout. The optimized FTI can reduce the light absorption on the FTI interface, and it enhances the PDE over 5 %.
We also develop high-resolution and high-dynamic-range (DR) photon counting image sensor by reducing the SPAD pixel size and power consumption. We fast demonstrated extrapolating architecture to decreasing counter bit size and power consumption by limiting the counting number even under the high incident optical power with 12.24-μm-pitch pixel [4]. The pixel-pitch is shrunk to 3.36 μm only with 8 bit in-pixel counter by employing a clustered multi-cycle clocked recharging (CMCR), intermediate most-significant-bit read out (MSB-Read) and Amplitude limitation with clipping transistor (Fig.3) [11]. The CMCR can limit the maximum counting photon and non-linear counting response. This can increase DR with suppressing power consumption. The MSB read expand the counter bit by detecting the number of the saturation of the in-pixel counter and storing the number in the SRAM outside the pixel array. This can increase bright light SNR over 30 dB. The clipping transistor limits the amplitude less than 0.8 V with maintaining SPAD bias voltage around 3 V. Most PFE circuits can be composed of low voltage transistor, resulting in the amplitude limitation and it can maximize the circuit size shrinking effect with 22-nm-node logic process. The 3.36-μm-pitch photon counting image sensor shows 120-dB HDR with 150 fps frame rate and 310 mW power consumption at 1 Mpix and 60 fps.
We also try to develop more advanced structure to shrink pixel pitch and increase robustness for voltage drop with large multiplication current for high-resolution photon counting. The embedded metal contact, power grid on deep trench pixel isolation and poly-Si resistor on the SPAD has been reported (Fig.4) [12] . The embedded metal contact suppresses edge breakdown by separate the anode and cathode region in a vertical direction. The poly-Si resistor can decrease the multiplication current by reducing amplitude of the voltage swing at input node of the output inverter. The embedded power grid contributes to decrease the resistance of the power supply wiring and to suppress voltage drop by multiplication current even in a large scale SPAD pixel array for the high-resolution photon counting.
The table I shows the comparison of the SPAD pixel performance, and the table II shows the comparison of the performance of photon-counting image sensor of our works and the others, respectively. We can achieve smaller SPAD pixel with highest PDE and low DCR. The smallest pitch photon counting image sensor is also achieved with competitive characteristics.
