Wafer Backside Fine 0.4µm Pitch Copper Interconnects for Multi Stacked Device Integration

Abstract

This paper presents fine copper interconnects with a line/space ratio of 0.2/0.2 µm formed on the middle wafer backside within a multi stacked structure. A flattened process was developed by optimizing thinning and through silicon via formation processes, and a suitable shape was obtained for the fine copper interconnects. Subsequently, excellent electrical characteristics and reliability of the copper interconnects were achieved in the 3D stacked structure.

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