Wafer Backside Fine Pitch Copper Interconnects and Low-profile Micro-bumps Pad Process for Multiple Chip-on-Wafer Stacking Structure

Abstract

We present a novel wafer backside Cu interconnect integration for a new chip stacking structure utilizing micro-bumps. This integration features a sub-micron thick, low-profile pad structure with a micro-bump connection pad height of less than 1 μm. The backside wiring achieves a fine pitch of 0.36 μm with a line/space ratio of 0.18/0.18 μm. The electrical characteristics and reliability of the Cu interconnect integration were evaluated using test elementary group structures. Results demonstrate that the micro-bumps and backside interconnects, including through-silicon vias, exhibit stable performance with low resistance and high reliability. This advanced Cu interconnect integration enabled the development of a multi-chip stacked backside-illuminated CMOS image sensor featuring a single-sided solder micro-bump connection.

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